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CD4541BC Programmable Timer
October 1987 Revised March 1999
CD4541BC Programmable Timer
General Description
The CD4541BC Programmable Timer is designed with a 16-stage binary counter, an integrated oscillator for use with an external capacitor and two resistors, output control logic, and a special power-on reset circuit. The special features of the power-on reset circuit are first, no additional static power consumption and second, the part functions across the full voltage range (3V-15V) whether power-on reset is enabled or disabled. Timing and the counter are initialized by turning on power, if the power-on reset is enabled. When the power is already on, an external reset pulse will also initialize the timing and counter. After either reset is accomplished, the oscillator frequency is determined by the external RC network. The 16-stage counter divides the oscillator frequency by any of 4 digitally controlled division ratios. s Oscillator frequency range DC to 100 kHz s Oscillator may be bypassed if external clock is available (apply external clock to pin 3) s Automatic reset initializes all counters when power turns on s External master reset totally independent of automatic reset operation s Operates at 2n frequency divider or single transition timer s Q/Q select provides output logic level flexibility s Reset (auto or master) disables oscillator during resetting to provide no active power dissipation s Clock conditioning circuit permits operation with very slow clock rise and fall times s Wide supply voltage range--3.0V to 15V s High noise immunity--0.45 VDD (typ.) s 5V-10V-15V parameter ratings s Symmetrical output characteristics s Maximum input leakage 1 A at 15V over full temperature range s High output drive (pin 8) min. one TTL load
Features
s Available division ratios 28, 210, 213, or 216 s Increments on positive edge clock transitions s Built-in low power RC oscillator (2% accuracy over temperature range and 10% supply and 3% over processing @ < 10 kHz)
Ordering Code:
Order Number CD4541BCN CD4541BCM Package Number N14A M14A Package Description 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
N.C.--Not connected
Top View
(c) 1999 Fairchild Semiconductor Corporation
DS006001.prf
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CD4541BC
Truth Table
Pin 0 5 6 9 10 Auto Reset Operating Timer Operational Output Initially Low after Reset Single Cycle Mode State 1 Auto Reset Disabled Master Reset On Output Initially High after Reset Recycle Mode
Division Ratio Table
Number of A B Counter Stages n 0 0 1 1 0 1 0 1 13 10 8 16 8192 1024 256 65536 Count 2n
Operating Characteristics
With Auto Reset pin set to a "0" the counter circuit is initialized by turning on power. Or with power already on, the counter circuit is reset when the Master Reset pin is set to a "1". Both types of reset will result in synchronously resetting all counter stages independent of counter state. The RC oscillator frequency is determined by the external RC network, i.e.: However, when B is "0", normal counting is interrupted and the 9th counter stage receives its clock directly from the oscillator (i.e., effectively outputting 28). The Q/Q select output control pin provides for a choice of output level. When the counter is in a reset condition and Q/Q select pin is set to a "0" the Q output is a "0". Correspondingly, when Q/Q select pin is set to a "1" the Q output is a "1". When the mode control pin is set to a "1", the selected count is continually transmitted to the output. But, with mode pin "0" and after a reset condition the RS flip-flop resets (see Logic Diagram), counting commences and after 2n-1 counts the RS flip-flop sets which causes the output to change state. Hence, after another 2n-1 counts the output will not change. Thus, a Master Reset pulse must be applied or a change in the mode pin level is required to reset the single cycle operation.
and RS 2 Rtc where RS 10 k The time select inputs (A and B) provide a two-bit address to output any one of four counter stages (28, 210, 213, and 216). The 2n counts as shown in the Division Ratio Table represent the Q output of the Nth stage of the counter. When A is "1", 216 is selected for both states of B.
Typical RC Oscillator Characteristics
RC Oscillator Frequency as a Function of RTC and C
Solid Line = RTC = 56 k, RS = 1 k and C = 1000 pF f = 10.2 kHz @ VDD = 10V and TA = 25 Dashed Line = RTC = 56 k, RS = 120 k and C = 1000 pF f = 7.75 kHz @ VDD = 10V and TA = 25 Line A: f as a function of C and (RTC = 56 k; RS = 120k Line B: f as a function of RTC and (C = 100 pF; R S = 2 R TC
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CD4541BC
Oscillator Circuit Using RC Configuration
Logic Diagram
VDD = Pin 14 VSS = Pin 7
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CD4541BC
Absolute Maximum Ratings(Note 1)
(Note 2) Supply Voltage (VDD ) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (soldering, 10 seconds) 260C (Note 2) 700 mW 500 mW -0.5V to +18V -0.5V to VDD +0.5V -65C to +150C
Recommended Operating Conditions (Note 2)
Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range 3V to 15V 0 to VDD -40C to +85C
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation. Note 2: VSS = 0V unless otherwise specified.
DC Electrical Characteristics
Symbol IDD Parameter Quiescent Device Current
Conditions VDD = 5V, VIN = VDD or VSS VDD = 10V, VIN = V DD or VSS VDD = 15V, VIN = V DD or VSS
-40C Min Max 20 40 80 0.05 0.05 0.05 4.95 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 2.32 3.18 12.4 5.1 2.69 10.5 -0.3 0.3 3.5 7.0 11.0 1.96 2.66 10.4 4.27 2.25 8.8 Min
+25C Typ 0.005 0.010 0.015 0 0 0 5 10 15 2 4 6 3 6 9 3.6 9.0 34.0 130 8.0 30.0 -10-5 10-5 -0.3 0.3 1.5 3.0 4.0 Max 20 40 80 0.05 0.05 0.05
+85C Min Max 150 300 600 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 1.6 2.18 8.50 3.5 1.85 7.22 -1.0 1.0
Units A A A V V V V V V V V V V V V mA mA mA mA mA mA A A
VOL
LOW Level Output Voltage
VDD = 5V VDD = 10V VDD = 15V |IO| < 1A
VOH
HIGH Level Output Voltage
VDD = 5V VDD = 10V VDD = 15V |IO| < 1 A
9.95 14.95
VIL
LOW Level Input Voltage
VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1.0V or 9.0V VDD = 15V, VO = 1.5V or 13.5V
VIH
HIGH Level Input Voltage
VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1.0V or 9.0V VDD = 15V, VO = 1.5V or 13.5V
IOL
LOW Level Output Current (Note 3)
VDD = 5V, VO = 0.4V VDD = 10V, VO = 0.5V VDD = 15V, VO = 1.5V VDD = 5V, VO = 2.5V VDD = 10V, VO = 9.5V VDD = 15V, VO = 13.5V VDD = 15V, VIN = 0V VDD = 15V, VIN = 15V
IOH
HIGH Level Output Current (Note 3)
IIN
Input Current
Note 3: IOH and IOL are tested one output at a time.
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CD4541BC
AC Electrical Characteristics
TA = 25C, CL = 50 pF (refer to test circuits) Symbol tTLH Parameter Output Rise Time
(Note 4)
Conditions VDD = 5V VDD = 10V VDD = 15V Min Typ 50 30 25 50 30 25 1.8 0.6 0.4 3.2 1.5 1.0 400 200 150 200 100 70 2.5 6.0 8.5 400 200 150 170 75 50 5.0 100 7.5 1.0 3.0 4.0 Max 200 100 80 200 100 80 4.0 1.5 1.0 8.0 3.0 2.0 Units ns ns ns ns ns ns s s s s s s ns ns ns MHz MHz MHz ns ns ns pF pF
tTHL
Output Fall Time
VDD = 5V VDD = 10V VDD = 15V
tPLH, tPHL
Turn-Off, Turn-On Propagation Delay, Clock to Q (28 Output)
VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V
tPHL, tPLH
Turn-On, Turn-Off Propagation Delay, Clock to Q (216 Output)
tWH(CL)
Clock Pulse Width
fCL
Clock Pulse Frequency
VDD = 5V VDD = 10V VDD = 15V
tWH(R)
MR Pulse Width
VDD = 5V VDD = 10V VDD = 15V
CI CPD
Average Input Capacitance Power Dissipation Capacitance (Note 5)
Any Input
Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note: AN-90.
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CD4541BC
Test Circuits and Waveforms
Power Dissipation Test Circuit and Waveforms Switching Time Test Circuit and Waveforms
(Rtc and Ctc outputs are left open)
C
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CD4541BC
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
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CD4541BC Programmable Timer
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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